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1. general description the pca9574 is a cmos device that provides 8 bits of general purpose parallel input/output (gpio) expansion in low voltage processor and handheld battery powered mobile applications and was developed to enhance the nxp family of i 2 c-bus i/o expanders. the improvements include lower supply current, lower operating voltage of 1.1 v to 3.6 v, dual and separate supply rails to allow voltage level translation anywhere between 1.1 v and 3.6 v, 400 khz clock frequ ency, and smaller packaging. any of the 8 i/o ports can be configured as an input or output independent of each other and default on start-up to inputs. i/o expanders provide a simple solution when additional i/os are needed while keeping interconnections to a minimum; for example in battery powered mobile applications and clam shell devices for interfacing to sensors, push buttons, keypad, etc. in addition to providing a flexible set of gpios, it simp lifies intercon nection of a processor running at one voltage level to i/o devices operating at a different (usually higher) voltage level. pca9574 has built-in level shifting feature that makes these devices extremely flexible in mixed signal environments where communication between incompatible i/os is required. the core of pca9574 can operate at a voltage as low as 1.1 v while the i/o bank can operate in the range 1.1 v to 3.6 v. bus hold with programmable on-chip pull-up or pull-down feature for i/os is also provided. the system master can enable the i/os as either inputs or outputs by writing to the i/o configuration register bits. the data for each in put or output is kept in the corresponding input or output register. the polarity of the r ead register can be inverted with the polarity inversion register (active high or active low operation). either a bus-hold function or pull-up/pull-down feature can be selected by programming corresponding registers. the bus-hold provides a valid lo gic level when the i/o bus is not actively driven. when bus-hold feature is not selected, the i/o po rts can be configured to have pull-up or pull-down by programming the pull-up/pull-down configuration register. an open-drain interrupt output pin (int ) allows monitoring of the input pins and is asserted each time a change occurs on an input port unless that port is masked (default = masked). a ?gpio all call? command allows programming multiple pca9574s at the same time even if they have different individual i 2 c-bus addresses. this allows optimal code programming when more than one device needs to be programmed with the same instruction or if all outputs need to be turned on or off at the same time. the internal power-on reset (por) or hardware reset pin (reset ) initializes the 8 i/os as inputs, sets the registers to their default values and initializes the device state machine. the i/o bank is held in its default state when the logic supply (v dd ) is off. one address select pin allows up to two pca9574 devices to be connected with two different addresses on the same i 2 c-bus. pca9574 8-bit i 2 c-bus and smbus, level translating, low voltage gpio with reset and interrupt rev. 3 ? 22 june 2011 product data sheet
pca9574 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 22 june 2011 2 of 31 nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio the pca9574 is available in tssop16 and hv qfn16 packages and is specified over the ? 40 ? c to +85 ? c industrial temperature range. 2. features and benefits ? 400 khz i 2 c-bus serial interface ? compliant with i 2 c-bus standard-mode (100 khz) ? separate supply rails for co re logic and i/o bank provides voltage level shifting ? 1.1 v to 3.6 v operation with level shifting feature ? very low standby current: < 1 ? a ? 8 configurable i/o pins that default to inputs at power-up ? outputs: ? totem pole: 1 ma source and 3 ma sink ? independently programmable 100 k ? pull-up or pull-down for each i/o pin ? open-drain active low interrupt (int ) output pin allows moni toring of logic level change of pins programmed as inputs ? inputs: ? programmable bus hold provides valid logic level when inputs are not actively driven ? programmable interrupt mask control for inpu t pins that do not require an interrupt when their states change or to prevent spurious interrupts default to mask at power-up ? polarity inversion register a llows inversion of the polarity of the i/o pins when read ? active low reset (reset ) input pin resets device to power-up default state ? gpio all call address allows programming of more than one device at the same time with the same parameters ? 2 programmable slave addresses using 1 address pin ? ? 40 ? c to +85 ? c operation ? esd protection exceeds 7000 v hbm per jesd22-a114 and 1000 v cdm per jesd22-c101 ? latch-up testing is done to jedec standard jesd78 which exceeds 100 ma ? packages offered: tssop16 and hvqfn16 3. applications ? cell phones ? media players ? multi voltage environments ? battery operated mobile gadgets ? motherboards ? servers ? raid systems ? industrial control ? medical equipment ? plcs
pca9574 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 22 june 2011 3 of 31 nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio ? gaming machines ? instrumentation and test measurement 4. ordering information 4.1 ordering options 5. block diagram table 1. ordering information type number package name description version PCA9574PW tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 pca9574bs hvqfn16 plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 3 ? 3 ? 0.85 mm sot758-1 table 2. ordering options type number topside mark temperature range PCA9574PW pca9574 t amb = ? 40 ? c to +85 ?c pca9574bs p74 t amb = ? 40 ? c to +85 ?c remark: all i/os are set to inputs at power-up and reset . fig 1. block diagram of pca9574 pca9574 power-on reset 002aad054 i 2 c-bus/smbus control input filter scl sda v dd input/ output ports p0 v ss 8-bit write pulse read pulse p2 p4 p6 p1 p3 p5 p7 lp filter v dd int a0 reset v dd(io)
pca9574 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 22 june 2011 4 of 31 nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio fig 2. simplified schematic of the i/os (p0 to p7) interrupt mask v dd(io) p0 to p7 output port register data configuration register dq ck q data from shift register write configuration pulse output port register dq ck write pulse polarity inversion register dq ck data from shift register write polarity pulse input port register dq ck read pulse input port register data polarity inversion register data 002aad066 ff data from shift register ff ff ff q1 q2 v ss to int bus-hold and pull-up/pull-down control esd protection diode 100 k v dd(io)
pca9574 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 22 june 2011 5 of 31 nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio 6. pinning information 6.1 pinning 6.2 pin description [1] hvqfn16 package die supply ground is connected to both v ss pin and exposed center pad. v ss pin must be connected to supply ground for proper device operation. for enhanced thermal, electric al, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the pcb in the thermal pad region. fig 3. pin configuration for tssop16 fig 4. pin configuration for hvqfn16 PCA9574PW 002aad052 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 int v dd a0 sda reset scl p0 p7 p1 p6 p2 p5 p3 p4 v ss v dd(io) 002aad053 pca9574bs transparent top view p2 p5 p1 p6 p0 p7 reset scl p3 v ss v dd(io) p4 a0 int v dd sda 4 9 3 10 2 11 1 12 5 6 7 8 16 15 14 13 terminal 1 index area table 3. pin description symbol pin type description tssop16 hvqfn16 int 1 15 o active low interrupt output; active low smbus alert output a0 2 16 i address input reset 3 1 i active low reset input p0 4 2 i/o input/output 0 p1 5 3 i/o input/output 1 p2 6 4 i/o input/output 2 p3 7 5 i/o input/output 3 v ss 86 [1] ground supply ground v dd(io) 9 7 power supply i/o bank supply voltage p4 10 8 i/o input/output 4 p5 11 9 i/o input/output 5 p6 12 10 i/o input/output 6 p7 13 11 i/o input/output 7 scl 14 12 i serial clock line sda 15 13 i/o serial data line v dd 16 14 power supply supply voltage
pca9574 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 22 june 2011 6 of 31 nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio 7. functional description 7.1 device address following a start condit ion the bus master must send the address of the slave it is accessing and the operation it wants to pe rform (read or write). the address of the pca9574 is shown in figure 5 . slave address pin a0 chooses 1 of 2 slave addresses: 40h or 42h. the last bit of the first byte defines the oper ation to be performed. when set to logic 1 a read is selected, while logi c 0 selects a write operation. 7.2 command register following the successful acknowled gement of the slave address + r/w bit, the bus master will send a byte to the pca9574, wh ich will be stored in the command register. the lowest 3 bits are used as a pointer to determine which register will be accessed. only a command register code with the 3 least signif icant bits equal to the 8 allowable values as defined in table 4 ? register summary ? will be acknowledged. re served or undefined command codes will not be acknowle dged. at power-up, this register def aults to 00h, with the ai bit set to ?0?, and th e lowest 3 bits set to ?0?. if the auto-increment flag is set (ai = 1), the 3 least significant bits of the command register are automatically incremented after a read or write. this allows the user to program and/or read the 8 command registers (listed in ta b l e 4 ) sequentially. it will then roll over to register 00h after the last register is accessed an d the selected registers will be overwritten or re-read. if the auto-increment flag is cleared (ai = 0), the 3 least significant bits are not incremented after data is read or written, only one regist er will be repeat edly read or written. fig 5. pca9574 device address 002aad055 0 1 0 0 0 0 a0 r/w fixed slave address hardware selectable reset state = 00h remark: the command register does not apply to software reset i 2 c-bus address. fig 6. command register 002aad056 ai x x x x d2 d1 d0 register address auto-increment flag
pca9574 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 22 june 2011 7 of 31 nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio 7.3 register definitions 7.4 writing to port registers data is transmitted to the pca9574 by sending the device address and setting the least significant bit to logic 0 (see figure 5 for device address). the command byte is sent after the address and determ ines which register will receiv e the data following the command byte. each 8-bit register may be updated independently of the other registers. 7.5 reading the port registers in order to read data from the pca9574, the bus master must first send the pca9574 address with the least significant bit set to a logic 0 (see figure 5 for device address). the command byte is sent after the address and determines which regi ster will be accessed. after a restart, the device address is sent again but this time, the least significant bit is set to logic 1. data from the register defined by the command byte will then be sent by the pca9574. data is clocked into the register on the falling edge of the acknowledge clock pulse. after the first byte is read, additio nal bytes may be read using the auto-increment feature. 7.5.1 register 0 - input port register this register is read-only. it reflects the in coming logic levels of the pins, regardless of whether the pin is defined as an input or an ou tput by the configuratio n register. writes to this register will be acknowle dged but will have no effect. the default ?x? is determined by the externally applied logic level. table 4. register summary register number d2 d1 d0 name type function 00h 0 0 0 in read only input port register 01h 0 0 1 invrt read/write pola rity inversion register 02h 0 1 0 bken read/write bus-hold enable register 03h 0 1 1 pupd read/write pull-up/p ull-down selector register 04h 1 0 0 cfg read/write port configuration register 05h 1 0 1 out read/write output port register 06h 1 1 0 msk read/write in terrupt mask register 07h 1 1 1 ints read only interrupt status register table 5. register 0 - input port register (address 00h) bit description bit symbol access value description 7 i0.7 read only x determined by externally applied logic level 6 i0.6 read only x 5 i0.5 read only x 4 i0.4 read only x 3 i0.3 read only x 2 i0.2 read only x 1 i0.1 read only x 0 i0.0 read only x
pca9574 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 22 june 2011 8 of 31 nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio 7.5.2 register 1 - polarity inversion register this register allows the user to invert the polar ity of the input port regi ster data. if a bit in this register is set (written with ?1?), the corresponding input port data is inverted. if a bit in this register is cleared (written with a ?0?) , the input port data po larity is retained. 7.5.3 register 2 - bus-hold/pull-up/pull-down enable register bit 0 of this register allows the user to en able/disable the bus-hold feature for the i/o pins. setting the bit 0 to logic 1 enables bus-hold feature for the i/o bank. in this mode, the pull-up/pull-downs will be disabl ed. setting the bit 0 to logic 0 disables bus-hold feature. bit 1 of this register allows the user to enable/disable pull-up/pull-downs on the i/o pins. setting the bit 1 to logic 1 enables selection of pull-up/pull-down using register 3. setting the bit 1 to logic 0 disables pull-up/pull-downs on the i/o pins and contents of register 3 will have no effect on the i/o. table 6. register 1 - polarity inversion register (address 01h) bit description legend: * default value. bit symbol access value description 7 n0.7 r/w 0* inverts polarity of input port register data 0 = input port register data retained (default value) 1 = input port register data inverted 6n0.6 r/w 0* 5n0.5 r/w 0* 4n0.4 r/w 0* 3n0.3 r/w 0* 2n0.2 r/w 0* 1n0.1 r/w 0* 0n0.0 r/w 0* table 7. register 2 - bus-hold/pull-up/pull- down enable register (address 02h) bit description legend: * default value. bit symbol access value description 7 e0.7 r/w x not used 6e0.6 r/w x 5e0.5 r/w x 4e0.4 r/w x 3e0.3 r/w x 2e0.2 r/w x 1 e0.1 r/w 0* allows the user to enab le/disable pull-up/pull-downs on the i/o pins 0 = disables pull-up/pull-downs on the i/o pins and contents of register 3 will have no effect on the i/o (default value) 1 = enables selection of pull-up/pull-down using register 3 0 e0.0 r/w 0* allows user to enable/disa ble the bus-hold f eature for the i/o pins 0 = disables bus-hold feature (default value) 1 = enables bus-hold feature
pca9574 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 22 june 2011 9 of 31 nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio 7.5.4 register 3 - pull-up/pull-down selector register when bus-hold feature is not selected and bit 1 of register 2 is set to logic 1, the i/o port can be configured to have pull-up or pull-down by programming the pull-up/pull-down register. setting a bit to logic 1 will select a 100 k ? pull-up resistor for that i/o pin. setting a bit to logic 0 will select a 100 k ? pull-down resistor for that i/o pin. if the bus-hold feature is enabled, writing to this regist er will have no effect on pull-up/pull-down selection. 7.5.5 register 4 - configuration register this register configures the dire ction of the i/o pins. if a bit in this register is set (written with logic 1), the corresponding port pin is enabled as an input with high-impedance output driver. if a bit in this register is clea red (written with logic 0), the corresponding port pin is enabled as an output. at reset, the device?s ports are inputs. table 8. register 3 - pull-up/pull-down selector register (address 03h) bit description legend: * default value. bit symbol access value description 7 p0.7 r/w 1* configures i/o port pin to have pull-up or pull-down when bus-hold feature not selected and bit 1 of register 2 is logic 1 0 = selects a 100 k ? pull-down resistor for that i/o pin 1 = selects a 100 k ? pull-up resistor for that i/o pin (default value) 6p0.6r/w1* 5p0.5r/w1* 4p0.4r/w1* 3p0.3r/w1* 2p0.2r/w1* 1p0.1r/w1* 0p0.0r/w1* table 9. register 4 - configuration register (address 04h) bit description legend: * default value. bit symbol access value description 7 c0.7 r/w 1* configures the direction of the i/o pins 0 = corresponding port pin enabled as an output 1 = corresponding port pin configured as input (default value) 6 c0.6 r/w 1* 5 c0.5 r/w 1* 4 c0.4 r/w 1* 3 c0.3 r/w 1* 2 c0.2 r/w 1* 1 c0.1 r/w 1* 0 c0.0 r/w 1*
pca9574 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 22 june 2011 10 of 31 nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio 7.5.6 register 5 - output port register this register is an output-only port. it reflects the outgoing logic levels of the pins defined as outputs by register 4. bit values in this register have no effect on pins defined as inputs. in turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. 7.5.7 register 6 - interrupt mask register all the bits of interrupt mask register are set to logic 1 upon power-on or software reset, thus disabling interrupts. interrupts may be enabled by setting corresponding mask bits to logic 0. table 10. register 5 - output port register (address 05h) bit description legend: * default value. bit symbol access value description 7 o0.7 r/w 0* reflects outgoing logic levels of pins defined as outputs by register 4 6o0.6 r/w 0* 5o0.5 r/w 0* 4o0.4 r/w 0* 3o0.3 r/w 0* 2o0.2 r/w 0* 1o0.1 r/w 0* 0o0.0 r/w 0* table 11. register 6 - interrupt mask register (address 06h) bit description legend: * default value. bit symbol access value description 7 m0.7 r/w 1* enable or disable interrupts 0 = enable interrupt 1 = disable interrupt (default value) 6m0.6 r/w 1* 5m0.5 r/w 1* 4m0.4 r/w 1* 3m0.3 r/w 1* 2m0.2 r/w 1* 1m0.1 r/w 1* 0m0.0 r/w 1*
pca9574 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 22 june 2011 11 of 31 nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio 7.5.8 register 7 - interrupt status register this register is read-only. it is used to identify the source of interrupt. remark: if the interrupts are masked, this register will return all zeros. 7.6 power-on reset when power is applied to v dd , an internal power-on reset (por) holds the pca9574 in a reset condition until v dd has reached v por . at that point, the rese t condition is released and the pca9574 registers and state machine will initialize to their default states. the power-on reset typically completes the reset and enables the part by the time the power supply is above v por . however, when it is required to reset the part by lowering the power supply, it is necessary to lower it below 0.2 v. 7.7 reset input a reset can be accomplished by holding the reset pin low for a minimum of t w(rst) . the pca9574 registers and i 2 c-bus state machin e will be held in their default state until the reset input is once again high. 7.8 software reset the software reset call allows all the devices in the i 2 c-bus to be reset to the power-up state value through a specific formatted i 2 c-bus command. to be pe rformed correctly, it implies that the i 2 c-bus is functional and that there is no device hanging the bus. the software reset sequence is defined as following: 1. a start command is sent by the i 2 c-bus master. 2. the reserved general call i 2 c-bus address ?0000 000? with the r/w bit set to 0 (write) is sent by the i 2 c-bus master. 3. the pca9574 device(s) acknowledge(s) after seeing the general call address ?0000 0000? (00h) only. if the r/w bit is set to logic 1 (read), no acknowledge is returned to the i 2 c-bus master. 4. once the general call address has been sent and acknowledged, the master sends 1 byte. the value of the byte must be equal to 06h.the pca9574 acknowledges this value only. if the byte is not equal to 06h, the pca9574 does not acknowledge it. if more than 1 byte of data is sent, the pca9574 does not acknowledge anymore. table 12. register 7 - interrupt status register (address 07h) bit description legend: * default value. bit symbol access value description 7 s0.7 read only 0* identifies source of interrupt 6 s0.6 read only 0* 5 s0.5 read only 0* 4 s0.4 read only 0* 3 s0.3 read only 0* 2 s0.2 read only 0* 1 s0.1 read only 0* 0 s0.0 read only 0*
pca9574 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 22 june 2011 12 of 31 nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio 5. once the right byte has been sent and correctly acknowledged, the master sends a stop command to end the software reset sequence: the pca9574 then resets to the default value (power-up value) and is ready to be addressed again within the specified bus free time. if the master sends a repeated start instead, no reset is performed. the i 2 c-bus master must interpret a non-acknowledge from the pca9574 (at any time) as a ?software reset abort?. the pca9574 does not initiate a software reset. 7.9 interrupt output (int ) the open-drain active low interrupt is activate d when one of the port pins changes state and the port pin is configured as an input and the interrupt on it is not masked. the interrupt is deactivated when the port pin input returns to its previous state or the input port register is read. it is highly recomme nded to program the msk register, and the cfg registers during the initialization sequence after power-up, since any change to them during normal mode operation may cause undesirable interrupt events to happen. remark: changing an i/o from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the input port register. only a read of the input port register that contains the bit( s) image of the input(s) that generated the interrupt clears the interrupt condition. 7.10 standby the pca9574 goes into standby when the i 2 c-bus is idle. standby s upply current is lower than 1.0 ? a (typical).
pca9574 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 22 june 2011 13 of 31 nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio 8. characteristics of the i 2 c-bus the i 2 c-bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up re sistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 8.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see figure 7 ). 8.1.1 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line while the clock is hi gh is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p) (see figure 8 ). 8.2 system configuration a device generating a message is a ?transmitter ?; a device receiving is the ?receiver?. the device that controls the message is the ?master? and the devices which are controlled by the master are the ?slaves? (see figure 9 ). fig 7. bit transfer mba607 data line stable; data valid change of data allowed sda scl fig 8. definition of start and stop conditions mba608 sda scl p stop condition s start condition
pca9574 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 22 june 2011 14 of 31 nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio 8.3 acknowledge the number of data bytes transferred betwe en the start and the stop conditions from transmitter to receiver is not limited. ea ch byte of eight bits is followed by one acknowledge bit. the acknowledge bit is a high level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must gen erate an acknowledge af ter the reception of each byte. also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transm itter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse; set-up time and hold time must be taken into account. a master receiver must signal an end of da ta to the transmitter by not generating an acknowledge on the last byte that has been cloc ked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. fig 9. system configuration 002aaa966 master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver sda scl i 2 c-bus multiplexer slave fig 10. acknowledgement on the i 2 c-bus 002aaa987 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
pca9574 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 22 june 2011 15 of 31 nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio 9. bus transactions data is transmitted to the pca9574 registers using ?write byte? transfers (see figure 11 and figure 12 ). data is read from the pca9574 regist ers using ?read byte? transfers (see figure 13 and figure 14 ). fig 11. write to output port register 0 a s slave address start condition r/w acknowledge from slave 002aad057 0000101 0 command byte a acknowledge from slave 12345678 scl 9 sda data 1 a write to port data out from port t v(q) acknowledge from slave data 1 valid data to port 10000a0 0 p stop condition fig 12. write to polarity inversion, bus-hold enable, pu ll-up/pull-down selector, configuration, interrupt mask and interrupt status registers 0 a s slave address start condition r/w acknowledge from slave 002aad058 0000xxx 0 command byte a acknowledge from slave 12345678 scl 9 sda data a data to register acknowledge from slave data to register 10000a0 0 p stop condition
pca9574 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 22 june 2011 16 of 31 nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio fig 13. read from register 10000a00 a s0 start condition r/w acknowledge from slave 002aad059 a acknowledge from slave sda a p command byte acknowledge from master data from register data (first byte) slave address stop condition s (repeated) start condition (cont.) (cont.) 10000a01 a 0 r/w acknowledge from slave slave address at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter na no acknowledge from master data from register data (last byte) this figure assumes the command byte has previously been programmed with 00h. transfer of data can be stopped at any moment by a stop condition. fig 14. read input port register 10000a01 a s0 slave address start condition r/w acknowledge from slave 002aad060 data from port a acknowledge from master sda 1 no acknowledge from master read from port data into port data from port data 1 data 4 int data 4 data 2 data 3 p stop condition t v(int) t rst(int) t h(d) t su(d) 2345678 scl 9 1
pca9574 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 22 june 2011 17 of 31 nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio 10. application design-in information 11. limiting values device address configured as 0100 0000b for this example. p0, p2, p3 configured as outputs. p1, p4, p5 configured as inputs. p6, p7 are not used and must be configured as outputs. fig 15. typical application pca9574 p0 p1 scl sda v dd scl sda p2 p3 v dd v ss master controller v ss v dd = 1.1 v to 3.6 v subsystem 1 (e.g., temp. sensor) int subsystem 2 (e.g., counter) reset controlled switch (e.g., cbt device) a b enable int v dd(io) int 1.1 k 2 k subsystem 3 (e.g., alarm system) alarm p4 p5 v dd(io) a0 p6 p7 1.6 k 1.6 k reset reset v dd(io) = 3.6 v 002aad061 subsystem 4 (e.g., rf module) ctrl table 13. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.5 +4.0 v v dd(io) input/output supply voltage v ss ? 0.5 v dd +0.5 v i i/o input/output current - ? 5m a i i input current - ? 20 ma i dd supply current - 90 ma i ss ground supply current - 90 ma p tot total power dissipation - 75 mw t stg storage temperature ? 65 +150 ?c t amb ambient temperature ? 40 +85 ?c
pca9574 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 22 june 2011 18 of 31 nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio 12. static characteristics table 14. static characteristics v dd = 1.1 v to 3.6 v; v dd(io) = 1.1 v to 3.6 v; v ss =0v; t amb = ? 40 ? c to +85 ? c; unless otherwise specified. symbol parameter conditions min typ max unit supplies v dd supply voltage 1.1 - 3.6 v v dd(io) input/output supply voltage 1.1 - v dd +0.5 v i dd supply current operating mode; v dd =3.6v; no load; f scl = 100 khz; i/o = inputs - 135 200 ? a i stbl low-level standby current standby mode; v dd = 3.6 v; no load; v i =v ss ; f scl = 0 khz; i/o = inputs -0.251 ? a i stbh high-level standby current standby mode; v dd = 3.6 v; no load; v i =v dd ; f scl = 0 khz; i/o = inputs -0.251 ? a v por power-on reset voltage no load; v i =v dd or v ss (rising v dd )- 0.81.0 v input scl; input/output sda v il low-level input voltage ? 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -3.6 v i ol low-level output current v ol =0.2v; v dd =1.1v 1 - - ma v ol =0.4v; v dd =2.3v 3 - - ma i l leakage current v i =v dd or v ss ? 1-+1 ? a c i input capacitance v i =v ss -61 0p f i/os v il low-level input voltage ? 0.5 - +0.3v dd(io) v v ih high-level input voltage 0.7v dd(io) -3.6 v i oh high-level output current v oh =0.9v; v dd(io) =1.1v 1 - - ma i ol low-level output current v ol =0.2v; v dd(io) =1.1v 1 - - ma v ol =0.5v; v dd(io) =3.6v 2 3 - ma v oh high-level output voltage i oh = ? 1ma; v dd(io) = 1.1 v 0.8 - - v i lih high-level input leakage current v dd(io) =3.6v; v i =v dd(io) --1 ? a i lil low-level input leakage current v dd(io) =3.6v; v i =v ss -- ? 1 ? a c i input capacitance - 3.7 5 pf c o output capacitance - 3.7 5 pf interrupt int i ol low-level output current v ol =0.4v; v dd =1.1v 3 - - ma select input a0; reset v il low-level input voltage ? 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -3.6 v i li input leakage current v i =v dd or v ss ? 1-+1 ? a
pca9574 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 22 june 2011 19 of 31 nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio fig 16. v oh at v dd =3.3v, v dd(io) =1.2v, i oh = ? 1 ma fig 17. v oh at v dd =3.3v, v dd(io) =3.3v, i oh = ? 1ma 1.0 2.0 3.0 v oh (v) 0 t amb (c) ?40 100 ?20 002aae765 0 20 40 60 80 4.0 v oh (v) 0 t amb (c) ?40 100 ?20 002aae766 0 20 40 60 80 1.0 2.0 3.0
pca9574 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 22 june 2011 20 of 31 nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio 13. dynamic characteristics [1] t vd;ack = time for acknowledgement signal from scl low to sda (out) low. [2] t vd;dat = minimum time for sda data out to be valid following scl low. [3] c b = total capacitance of one bus line in pf. table 15. dynamic characteristics v dd = 1.1 v to 3.6 v; v dd(io) = 1.1 v to 3.6 v; v ss =0v; t amb = ? 40 ? c to +85 ? c; unless otherwise specified. symbol parameter conditions standard-mode i 2 c-bus fast-mode i 2 c-bus unit min max min max f scl scl clock frequency 0 100 0 400 khz t buf bus free time between a stop and start condition 4.7 - 1.3 - ? s t hd;sta hold time (repeated) start condition 4.0 - 0.6 - ? s t su;sta set-up time for a repeated start condition 4.7 - 0.6 - ? s t su;sto set-up time for stop condition 4.0 - 0.6 - ? s t vd;ack data valid acknowledge time [1] 0.3 3.45 0.1 0.9 ? s t hd;dat data hold time 0 - 0 - ns t vd;dat data valid time [2] 300 - 50 - ns t su;dat data set-up time 250 - 100 - ns t low low period of the scl clock 4.7 - 1.3 - ? s t high high period of the scl clock 4.0 - 0.6 - ? s t f fall time of both sda and scl signals - 300 20 + 0.1c b [3] 300 ns t r rise time of both sda and scl signals - 1000 20 + 0.1c b [3] 300 ns t sp pulse width of spikes that must be suppressed by the input filter -50 - 50ns port timing t v(q) data output valid time - 200 - 200 ns t su(d) data input set-up time 150 - 150 - ns t h(d) data input hold time 1 - 1 - ? s interrupt timing t v(int) valid time on pin int -4 - 4 ? s t rst(int) reset time on pin int -4 - 4 ? s reset t w(rst) reset pulse width 6 - 6 - ns t rec(rst) reset recovery time 0 - 0 - ns t rst(sda) sda reset time figure 19 - 450 - 450 ns t rst(gpio) gpio reset time figure 19 - 450 - 450 ns
pca9574 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 22 june 2011 21 of 31 nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio fig 18. definition of timing t sp t buf t hd;sta p p s t low t r t hd;dat t f t high t su;dat t su;sta sr t hd;sta t su;sto sda scl 002aaa986 fig 19. reset timing sda scl 002aad062 t rst 50 % 30 % 50 % 50 % 50 % t rec(rst) t w(rst) reset p0 to p7 output off start t rst ack or read cycle
pca9574 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 22 june 2011 22 of 31 nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio 14. test information r l = load resistance. c l = load capacitance includes jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generators. (1) for sda, no 500 ? pull-down. fig 20. test circuitry for switching times pulse generator v o c l 50 pf r l 500 002aad582 r t v i v dd dut 2v dd open v ss 500 (1)
pca9574 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 22 june 2011 23 of 31 nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio 15. package outline fig 21. package outline sot403-1 (tssop16) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot403-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 18 16 9 a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 a max. 1.1 pin 1 index
pca9574 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 22 june 2011 24 of 31 nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio fig 22. package outline sot758-1 (hvqfn16) terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 3.1 2.9 d h 1.75 1.45 y 1 3.1 2.9 1.75 1.45 e 1 1.5 e 2 1.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot758-1 mo-220 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot758-1 hvqfn16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 3 x 3 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 58 16 13 12 9 4 1 x d e c b a e 2 02-03-25 02-10-21 terminal 1 index area 1/2 e 1/2 e ac c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1)
pca9574 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 22 june 2011 25 of 31 nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio 16. handling information all input and output pins are protected ag ainst electrostatic discharge (esd) under normal handling. when handling ensure that the appropriate precautions are taken as described in jesd625-a or equivalent standards. 17. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 17.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 17.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 17.3 wave soldering key characteristics in wave soldering are:
pca9574 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 22 june 2011 26 of 31 nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities 17.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 23 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 1 6 and 17 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 23 . table 16. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 17. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pca9574 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 22 june 2011 27 of 31 nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 18. abbreviations msl: moisture sensitivity level fig 23. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 18. abbreviations acronym description cbt cross bar technology cdm charged-device model cmos complementary metal-oxide semiconductor dut device under test esd electrostatic discharge gpio general purpose input/output hbm human body model i/o input/output i 2 c-bus inter-integrated circuit bus ic integrated circuit led light emitting diode lp low pass pcb printed-circuit board plc programmable logic controller por power-on reset raid redundant array of independent discs smbus system management bus
pca9574 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 22 june 2011 28 of 31 nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio 19. revision history table 19. revision history document id release date data sheet status change notice supersedes pca9574 v.3 20110622 product data sheet - pca9574 v.2 modifications: ? removed hxqfn16u package option (t ype number pca9574hr; sot1046-1) ? section 2 ? features and benefits ? , 13th bullet: deleted ?500 v mm per jesd22-a115? pca9574 v.2 20090727 product data sheet - pca9574 v.1 pca9574 v.1 20080515 product data sheet - -
pca9574 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 22 june 2011 29 of 31 nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio 20. legal information 20.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 20.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 20.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
pca9574 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 3 ? 22 june 2011 30 of 31 nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 20.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 21. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors pca9574 8-bit i 2 c-bus and smbus, level tran slating, low volage gpio ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 22 june 2011 document identifier: pca9574 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 22. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 2 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 functional description . . . . . . . . . . . . . . . . . . . 6 7.1 device address . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.2 command register . . . . . . . . . . . . . . . . . . . . . . 6 7.3 register definitions . . . . . . . . . . . . . . . . . . . . . . 7 7.4 writing to port registers. . . . . . . . . . . . . . . . . . . 7 7.5 reading the port registers . . . . . . . . . . . . . . . . 7 7.5.1 register 0 - input port register . . . . . . . . . . . . . 7 7.5.2 register 1 - polarity inversion register . . . . . . . 8 7.5.3 register 2 - bu s-hold/pull-up/pull-down enable register . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.5.4 register 3 - pull-up/pull-down selector register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.5.5 register 4 - configuration register . . . . . . . . . . 9 7.5.6 register 5 - output port register . . . . . . . . . . . 10 7.5.7 register 6 - interrupt mask register . . . . . . . . 10 7.5.8 register 7 - interrupt stat us register . . . . . . . . 11 7.6 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 11 7.7 reset input . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.8 software reset. . . . . . . . . . . . . . . . . . . . . . . . . 11 7.9 interrupt output (int ) . . . . . . . . . . . . . . . . . . . 12 7.10 standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8 characteristics of the i 2 c-bus . . . . . . . . . . . . 13 8.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.1.1 start and stop conditions . . . . . . . . . . . . . 13 8.2 system configuration . . . . . . . . . . . . . . . . . . . 13 8.3 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 14 9 bus transactions . . . . . . . . . . . . . . . . . . . . . . . 15 10 application design-in information . . . . . . . . . 17 11 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17 12 static characteristics. . . . . . . . . . . . . . . . . . . . 18 13 dynamic characteristics . . . . . . . . . . . . . . . . . 20 14 test information . . . . . . . . . . . . . . . . . . . . . . . . 22 15 package outline . . . . . . . . . . . . . . . . . . . . . . . . 23 16 handling information. . . . . . . . . . . . . . . . . . . . 25 17 soldering of smd packages . . . . . . . . . . . . . . 25 17.1 introduction to soldering . . . . . . . . . . . . . . . . . 25 17.2 wave and reflow soldering. . . . . . . . . . . . . . . 25 17.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 25 17.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 26 18 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 27 19 revision history . . . . . . . . . . . . . . . . . . . . . . . 28 20 legal information . . . . . . . . . . . . . . . . . . . . . . 29 20.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 29 20.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 20.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 29 20.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 30 21 contact information . . . . . . . . . . . . . . . . . . . . 30 22 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

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